TDMAS=0, RDMAS=0
UART Control Register 5
| RESERVED | no description available |
| RDMAS | Receiver Full DMA Select 0 (0): If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. 1 (1): If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. |
| RESERVED | no description available |
| TDMAS | Transmitter DMA Select 0 (0): If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. 1 (1): If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. |